[Book] SystemVerilog for Verification Third Edition

Thảo luận trong 'ASIC CĂN BẢN' bắt đầu bởi duongnt, 6 Tháng bảy 2017.

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  1. duongnt

    By:duongntin: 6 Tháng bảy 2017
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    9 Tháng ba 2017
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    What is this Book About?
    This book should be the fi rst one you read to learn the SystemVerilog verifi cation language constructs. It describes how the language works and includes many examples on how to build a basic coverage-driven, constrained-random, layered testbench using Object-Oriented Programming (OOP). The book has many guidelines on building testbenches, to help you understand how and why to use classes, randomization, and functional coverage. Once you have learned the language, pickup some of the methodology books listed in the References section for more information on building a testbench.

    Chapter 1, Verification Guidelines.

    Chapter 2, Data Types.

    Chapter 3, Procedural Statements and Routines.

    Chapter 4, Connecting the Testbench and Design.

    Chapter 5, Basic OOP .

    Chapter 6, Randomization .

    Chapter 7, Threads and Interprocess Communication.

    Chapter 8, Advanced OOP and Testbench Guidelines.

    Chapter 9, Functional Coverage.

    Chapter 10 ,Advanced Interfaces.

    Chapter 11, A Complete SystemVerilog Testbench.

    Chapter 12, Interfacing with C / C++.

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